View CYM1851V33_322159.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

3
PRELIMINARY
CYM1851V33
1,024K x 32 3.3V Static RAM Module
Features
* High-density 3.3V 32-megabit SRAM module * 32-bit Standard Footprint supports densities from 16K x 32 through 1M x 32 * High-speed SRAMs -- Access time of 12 ns * Low active power -- 3.3W (max.) at 12 ns * 72 pins * Available in ZIP, SIMM, or angled SIMM format packages mounted on an epoxy laminate substrate. Four chip selects are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. The CYM1851V33 is designed for use with standard 72-pin SIMM sockets. The pinout is downward compatible with the 64-pin JEDEC ZIP/SIMM module family (CYM1821, CYM1831, CYM1836, and CYM1841). Thus, a single motherboard design can be used to accommodate memory depth ranging from 16K words (CYM1821) to 1,024K words (CYM1851). The CYM1851V33 is offered in vertical and angled SIMM configurations and both are available with either tin-lead or 10 micro-inches of gold flash on the edge contacts. Presence detect pins (PD 0-PD3) are used to identify module memory density in applications where modules with alternate word depths can be interchanged.
Functional Description
The CYM1851V33 is a 3.3V high-performance 32-megabit static RAM module organized as 1,024K words by 32 bits. This module is constructed from eight 1,024K x 4 SRAMs in SOJ
Logic Block Diagram
PD0 PD1 PD2 PD3 GND OPEN GND OPEN
Pin Configuration
ZIP/SIMM Top View
A0-A19 OE WE 1M x 4 SRAM CS1 1M x 4 SRAM CS2 1M x 4 SRAM CS3 1M x 4 SRAM CS
4
20
4
I/O0 - I/O3
1M x 4 SRAM
4
I/O4-I/O7
4
I/O8 - I/O11
1M x 4 SRAM
4
I/O12-I/O15
4
I/O16 - I/O19
1M x 4 SRAM
4
I/O20-I/O23
NC PD3 PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 WE A14 CS1 CS3 A16 GND I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND A19 NC
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
NC PD2 GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND A15 CS2 CS4 A17 OE I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31 A18 NC
4
I/O24 - I/O27
1M x 4 SRAM
I/O28-I/O31
4
1851V33-1
1851V33-2
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Apr 1998 - Revised June 30, 1998
PRELIMINARY
Selection Guide
1851V33-12 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA)
Shaded area contains advance information.
CYM1851V33
1851V33-15 15 1250 520
1851V33-20 20 1100 480
1851V33-25 25 1100 480
1851V33-35 35 1100 480
12 1450 540
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -55C to +125C Ambient Temperature with Power Applied ............................................... -10C to +85C Supply Voltage to Ground Potential ............... -0.5V to +4.6V DC Voltage Applied to Outputs in High Z State ................................................ -0.5V to +VCC DC Input Voltage............................................ -0.5V to +4.6V
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 3.3V +10%/ -5%
Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current GND < V I < V CC GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA, CSN < VIL, f = fMAX -12 -15 -20, -25, -35 ISB1 Automatic CS Power-Down Current[1] Max. VCC, CS > V IH, Min. Duty Cycle = 100% -12 -15 -20, -25, -35 ISB2 Automatic CS Power-Down Current[1] Max. VCC, CS > V CC - 0.2V, VIN > VCC - 0.2V, or VIN < 0.2V Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 4.0 mA 2.0 -0.3 -16 -10 Min. 2.4 0.4 VCC + 0.3 0.8 +16 +10 1450 1250 1100 540 520 480 270 Max. Unit V V V V A A mA mA mA mA mA mA mA
Shaded area contains advance information.
Capacitance[2]
Parameter CINA CINB COUT Description Input Capacitance (WE, OE, A 0-19) Input Capacitance (CS) Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 40 10 8 Unit pF pF pF
Notes: 1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 2. Tested on a sample basis.
2
PRELIMINARY
AC Test Loads and Waveforms
R1 317 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 351 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 351 R1 317 3.0V 90% GND 5 ns
1851V33-3
CYM1851V33
ALL INPUT PULSES 90% 10% 5 ns
1851V33-4
10%
(a)
(b)
Equivalent to: OUTPUT
THEVENIN 167
EQUIVALENT 1.73V
Switching Characteristics Over the Operating Range[3]
1851V33-12 Parameter READ CYCLE tRC tAA tOHA tACS tDOE tLZOE tHZOE tLZCS tHZCS tPD WRITE CYCLE tWC tSCS tAW tHA tSA tPWE tSD tHD tLZWE tHZWE
[6]
1851V33-15 Min. 15 Max. Unit ns 15 3 15 8 0 8 3 8 15 15 10 10 0 1 12 8 1 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 ns
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CS LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CS LOW to Low Z
[4] [4, 5]
Min. 12
Max.
12 3 12 7 0 7 3 7 12 12 9 9 0 1 10 7 1 3 0 7
CS HIGH to High Z
CS HIGH to Power-Down Write Cycle Time CS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z
[5]
0
Shaded area contains advance information.
3
PRELIMINARY
Switching Characteristics Over the Operating Range[3] (continued)
1851V33-20 Parameter READ CYCLE tRC tAA tOHA tACS tDOE tLZOE tHZOE tLZCS tHZCS tPD tWC tSCS tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CS LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CS LOW to Low Z
[4] [4, 5]
CYM1851V33
1851V33-25 Min. 25 Max.
1851V33-35 Min. 35 Max. Unit ns 35 3 35 18 0 15 3 15 35 35 30 30 3 2 30 20 2 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 ns
Description
Min. 20
Max.
20 3 20 12 0 10 3 10 20 20 17 17 3 2 15 12 2 3 0 12 25 20 20 3 2 20 15 2 3 0 3 0 3
25 25 15 12 12 25
CS HIGH to High Z
CS HIGH to Power-Down Write Cycle Time CS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z
[5]
WRITE CYCLE[6]
12
0
Switching Waveforms
Read Cycle No. 1 [7,8]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
1851V33-5
Notes: 3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed and not 100% tested. 5. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage. 6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 7. WE is HIGH for read cycle. 8. Device is continuously selected, CS = VIL, and OE= VIL .
4
PRELIMINARY
Switching Waveforms (continued)
Read Cycle No. 2 [7,9]
tRC CS tACS OE tDOE tLZOE HIGH IMPEDANCE DATA OUT tLZCS tPU V CC SUPPLY CURRENT 50% DATA VALID tHZOE tHZCS
CYM1851V33
HIGH IMPEDANCE
tPD ICC 50% ISB
1851V33-6
Write Cycle No. 1 (WE Controlled)
[6]
tWC ADDRESS tSCS CS tAW tSA WE tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED
1851V33-7
tHA tPWE
tHD
tLZWE HIGH IMPEDANCE
Note: 9. Address valid prior to or coincident with CS transition LOW.
5
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 2 (CS Controlled)
[6,10]
CYM1851V33
tWC ADDRESS tSA CS tAW tPWE WE tSD DATA IN DATA VALID tHZWE DATA OUT HIGH IMPEDANCE DATA UNDEFINED
1851V33-8
tSCS
tHA
tHD
Note: 10. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Truth Table
CS H L L L WE X H L H OE X L X H Inputs/Output High Z Data Out Data In High Z Read Write Deselect Mode Deselect/Power-Down
Ordering Information
Speed (ns) 12 Ordering Code CYM1851V33PM-12C CYM1851V33P8-12C CYM1851V33PN-12C CYM1851V33P6-12C CYM1851V33PZ-12C 15 CYM1851V33PM-15C CYM1851V33P8-15C CYM1851V33PN-15C CYM1851V33P6-15C CYM1851V33PZ-15C
Shaded area contains advance information.
Package Type PM04 PM04 PN04 PN04 PZ09 PM04 PM04 PN04 PN04 PZ09
Package Type 72-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module (gold contacts) 72-Pin Plastic Angled SIMM Module 72-Pin Plastic Angled SIMM Module (gold contacts) 72-Pin Plastic ZIP Module 72-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module (gold contacts) 72-Pin Plastic Angled SIMM Module 72-Pin Plastic Angled SIMM Module (gold contacts) 72-Pin Plastic ZIP Module
Operating Range Commercial
Commercial
6
PRELIMINARY
Ordering Information (continued)
Speed (ns) 20 Ordering Code CYM1851V33PM-20C CYM1851V33P8-20C CYM1851V33PN-20C CYM1851V33P6-20C CYM1851V33PZ-20C 25 CYM1851V33PM-25C CYM1851V33P8-25C CYM1851V33PN-25C CYM1851V33P6-25C CYM1851V33PZ-25C 35 CYM1851V33PM-35C CYM1851V33P8-35C CYM1851V33PN-35C CYM1851V33P6-35C CYM1851V33PZ-35C Document #: 38-M-00090-A Package Type PM04 PM04 PN04 PN04 PZ09 PM04 PM04 PN04 PN04 PZ09 PM04 PM04 PN04 PN04 PZ09 Package Type 72-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module (gold contacts) 72-Pin Plastic Angled SIMM Module 72-Pin Plastic Angled SIMM Module (gold contacts) 72-Pin Plastic ZIP Module 72-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module (gold contacts) 72-Pin Plastic Angled SIMM Module 72-Pin Plastic Angled SIMM Module (gold contacts) 72-Pin Plastic ZIP Module 72-Pin Plastic SIMM Module 72-Pin Plastic SIMM Module (gold contacts) 72-Pin Plastic Angled SIMM Module 72-Pin Plastic Angled SIMM Module (gold contacts) 72-Pin Plastic ZIP Module
CYM1851V33
Operating Range Commercial
Commercial
Commercial
Package Diagrams
72-Pin Plastic SIMM Module PM04
72-Pin Plastic Angled SIMM Module PN04
7
PRELIMINARY
Package Diagrams (continued)
72-Pin Plastic ZIP Module PZ09
CYM1851V33
(c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

▲Up To Search▲

Price & Availability of CYM1851V33

	To Download CYM1851V33 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .